蜗窝科技

@tigger：一直觉得三星的代码写的不好……

samsung的这个pin跟gpio系统耦合的太严重了，代码架构看起来也不整洁，我想这也是楼主不想写的原因吧。代码看起来没有快感。

@stxinu：欢迎欢迎，多交流~~

楼主大牛，最近项目涉及到中断，偶然机会找到楼主中断专题相关文章，受益良多。谢谢！

最近刚做了个小站http://x-slam.com，主要是跟Linux相关的，希望能互相交流学习。

穿戴设备的提醒功能，我觉得还是不错，省的漏电话。因为体积问题，目前的续航能力都不是太好。 如果单纯的采集健康指标，手机就可以了。2010年时候做过一款手机，集成以色列的芯片，心跳、血氧、血糖,都能在手机上测试，主要就是集成进很多sensor。

@chunhai：我们在PPI的mode上有些不同的意见，我又仔细的阅读了GIC的规范文档，这份文档是这样描述的： 1-N model的定义是 Only one processor handles this interrupt. The system must implement a mechanism to determine which processor handles an interrupt that is programmed to target more than one processor. N-N model的定义是：All processors receive the interrupt independently. When a processor acknowledges the interrupt,the interrupt pending state is cleared only for that processor. The interrupt remains pending for the other processors. 我觉得PPI是符合N-N model定义的，各个processor是独立的收到中断的，PPI的register是banked，因此，ack其一不影响其他。因此我认为PPI是N-N mode。 在ARM官方发布的IHI0048B_b_gic_architecture_specification.pdf的3.1.1章节，有下面的内容： In a multiprocessor implementation the GIC handles: • software generated interrupts (SGIs) using the GIC N-N model • peripheral (hardware) interrupts using the GIC 1-N model. PPI属于peripheral interrupt，因此看起来你是对的，但是在该文档的3.2章节，有一处的描述如下： In a multiprocessor implementation, the GIC handles: — PPIs and SGIs using the GIC N-N model, where the acknowledgement of an interrupt by one processor has no effect on the state of the interrupt on other CPU interfaces — SPIs using the GIC 1-N model, where the acknowledgement of an interrupt by one processor removes the pending status of the interrupt on any other targeted processors 从这里看，我的结论是对的。 不过，我认为我们不必纠结于属于哪一个mode，关键是理解PPI的硬件行为即可。

你们三个大牛的对话，看后受益匪浅，现在改用delay_work。谢谢你们！Thank you！ PS：这个网站真好，里面好多知识，小僧继续默默修行 -_-

@linuxer：多谢，你很严谨，希望以后能多跟你交流。

@chunhai：我也是仔细的查了一下。 SPI PPI属于 peripheral interrupts 也是是SPI PPI，N-1的意思我是这样理解的。只有一个CPU 去响应中断，其他的CPU 是不响应中断的，即使是其他的CPU同时响应了，但是过不到锁，也是只有一个CPU 处理中断。 不知我的理解对吗？ In a multiprocessor implementation, the GIC handles: — SGIs using an N-N model, where the acknowledgement of an interrupt by one processor has no effect on the state of the interrupt on other CPU interfaces — peripheral interrupts using a 1-N model, where the acknowledgement of an interrupt by one processor removes the pending status of the interrupt on any other targeted processors, see Implications of the 1-N model on page 3-8. In a multiprocessor implementation, the GIC uses a 1-N model to handle peripheral interrupts that target more than one processor. This means that when the GIC recognizes an interrupt acknowledge from one of the target processors it clears the pending state of the interrupt on all the other targeted processors. This model means an interrupt can be handled by the first available processor. However, the interrupt might generate an interrupt exception on more than one of the targeted processors, for example if two of the targeted processors recognize the interrupt exception request from the GIC at similar times. When multiple target processors attempt to acknowledge the interrupt, the following can occur: • A processor reads the ICCIAR and obtains the interrupt ID of the interrupt to be serviced, see Interrupt Acknowledge Register (ICCIAR) on page 4-56. More than one target processor might have obtained this interrupt ID, if the processors read their ICCIARs at very similar times. The system Interrupt Handling and Prioritization ARM IHI 0048A Copyright © 2008 ARM Limited. All rights reserved. 3-9 Unrestricted Access Non-Confidential might require software on the target processors to ensure that only one processor runs its interrupt service routine. A typical mechanism to achieve this is implementing a lock on the interrupt service routine (ISR), in shared memory. This might operate as follows: — each target processor that obtains the interrupt ID from its read of the ICCIAR runs a semaphore routine, attempting to obtain a lock on the ISR corresponding to the specified ID value — if a processor fails to obtain the lock it does no further processing of the interrupt, but writes the interrupt ID to its ICCEOIR, see End of Interrupt Register (ICCEOIR) on page 4-59 — the processor that obtains the lock handles the interrupt and then writes the interrupt ID to its ICCEOIR. • A processor reads the ICCIAR and obtains the interrupt ID 1023, indicating a spurious interrupt. The processor can return from its interrupt service routine without writing to its ICCEOIR. The spurious interrupt ID indicates that the original interrupt is no longer pending, typically because another target processor is handling it.