zoro
    请问框图是用什么软件画的啊
    Linux MMC framework(1)_软件架构  发表时间:2017-03-25 23:55
    wowo
    @lgp802a:我也没有做过高通平台,不太了解。 不过调频有时确实需要用户空间参与的,因为kernel虽然知道load,但不知道用户的关注点:性能还是功耗?
    linux cpufreq framework(4)_cpufreq governor  发表时间:2017-03-24 21:33
    wowo
    @Qwerty:多谢建议,确实,有时候写的时候比较着急,就没有详细的加这些链接,以后尽量注意~~~
    X-004-UBOOT-串口驱动移植(Bubblegum-96平台)  发表时间:2017-03-24 21:27
    lgp802a
    感谢wowo这么详尽的分析。实际应用中,比如高通平台。频率调整需要user space参与吗?今天和同事讨论,他说高通平台需要user space的服务根据应用场景来控制。而我理解是只需要governor计算出load,根据策略调整,不需要user space参与。没搞过高通,不知道实际怎么一回事。
    linux cpufreq framework(4)_cpufreq governor  发表时间:2017-03-24 20:53
    Qwerty
    @Qwerty:不好意思,找到了。楼主以后如果有引用之前分析过的部分,可以加个链接。:)
    X-004-UBOOT-串口驱动移植(Bubblegum-96平台)  发表时间:2017-03-24 17:08
    Qwerty
    你好。没有写过驱动,进展到此处,应该去看哪部分子系统的分析?
    X-004-UBOOT-串口驱动移植(Bubblegum-96平台)  发表时间:2017-03-24 17:03
    zhusbj
    针对 MMU OFF / Cache ON有一些不同的见解。摘自ARMv8-A TRM --------------------------------------------------------- Behavior when stage 1 address translation is disabled When a stage 1 address translation is disabled, memory accesses that would otherwise be translated by that stage of translation are treated as follows: Non-secure EL1 and EL0 accesses if the HCR_EL2.DC bit is set to 1 For the Non-secure EL1&0 translation regime, when the value of HCR_EL2.DC is 1, the stage 1 translation assigns the Normal Non-shareable, Inner Write-Back Read-Write-Allocate, Outer Write-Back Read-Write-Allocate memory attributes. Note This applies for both instruction and data accesses. All other accesses For all other accesses, when stage 1 address translation is disabled, the assigned attributes depend on whether the access is a data access or an instruction access, as follows: Data access The stage 1 translation assigns the Device-nGnRnE memory type. Instruction access The stage 1 translation assigns the Normal memory attribute, with the cacheability and shareability attributes determined by the value of the SCTLR.I bit for the translation regime, as follows: When the value of I is 0 The stage 1 translation assigns the Non-cacheable and Outer Shareable attributes. When the value of I is 1 The stage 1 translation assigns the Cacheable, Inner Write-Through no Write-Allocate Read-Allocate, Outer Write-Through no Write-Allocate Read Allocate Outer Shareable attribute. --------------------------------------------------------- DC, bit [12] Default Cacheable. When this bit is set to 1, this causes: • The SCTLR_EL1.M bit to behave as 0 when in the Non-secure state for all purposes other than reading the value of the bit. • The HCR_EL2.VM bit to behave as 1 when in the Non-secure state for all purposes other than reading the value of the bit. The memory type produced by the first stage of translation used by EL1 and EL0 is Normal Non-Shareable, Inner WriteBack Read-WriteAllocate, Outer WriteBack Read-WriteAllocate. When this bit is 0 and the stage 1 MMU is disabled, the default memory attribute for Data accesses is Device-nGnRnE. This bit is permitted to be cached in a TLB. --------------------------------------------------------- 楼主的解释需要一个前提条件,就是HCR_EL2.DC 必须已经置1。但是这个bit默认值很可能是0,并且代码中也没有置1的操作,所以memory的属性应该是Device-nGnRnE for data access。对于 instruction access,取决于SCTLR.I bit。
    ARM64的启动过程之(一):内核第一个脚印  发表时间:2017-03-24 16:01
    justin-wjb
    @SleepDeXiang:你的回复太逗了~~~
    linux内核中的GPIO系统之(2):pin control subsystem  发表时间:2017-03-24 15:18
    zhusbj
    从英文表述来看,因为device属性的memory store指令和cache 指令没有数据依赖关系,所以可以乱序执行。 但是源代码中明显是考虑到了 cache on的情况,否则也不必要在最后调用一下 cache invalidate操作。 所以我觉得在能保证 non-cacheable 的情况下,可以不必插入dmb指令。
    ARM64的启动过程之(一):内核第一个脚印  发表时间:2017-03-24 15:16
    linuxer
    @adance:其实我对这些概念也不是理解的特别透彻,但是我的理解就是memory barrier和cache coherence protocol是两码事。
    Linux内核同步机制之(三):memory barrier  发表时间:2017-03-23 16:33

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