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   1: /* arch/arm64/include/asm/cpu_ops.h */

   2: /**

   3:  * struct cpu_operations - Callback operations for hotplugging CPUs.

   4:  *

   5:  * @name:       Name of the property as appears in a devicetree cpu node's

   6:  *              enable-method property.

   7:  * @cpu_init:   Reads any data necessary for a specific enable-method from the

   8:  *              devicetree, for a given cpu node and proposed logical id.

   9:  * @cpu_init_idle: Reads any data necessary to initialize CPU idle states from

  10:  *              devicetree, for a given cpu node and proposed logical id.

  11:  * @cpu_prepare: Early one-time preparation step for a cpu. If there is a

  12:  *              mechanism for doing so, tests whether it is possible to boot

  13:  *              the given CPU.

  14:  * @cpu_boot:   Boots a cpu into the kernel.

  15:  * @cpu_postboot: Optionally, perform any post-boot cleanup or necesary

  16:  *              synchronisation. Called from the cpu being booted.

  17:  * @cpu_disable: Prepares a cpu to die. May fail for some mechanism-specific

  18:  *              reason, which will cause the hot unplug to be aborted. Called

  19:  *              from the cpu to be killed.

  20:  * @cpu_die:    Makes a cpu leave the kernel. Must not fail. Called from the

  21:  *              cpu being killed.

  22:  * @cpu_kill:  Ensures a cpu has left the kernel. Called from another cpu.

  23:  * @cpu_suspend: Suspends a cpu and saves the required context. May fail owing

  24:  *               to wrong parameters or error conditions. Called from the

  25:  *               CPU being suspended. Must be called with IRQs disabled.

  26:  */

  27: struct cpu_operations {

  28:         const char      *name;

  29:         int             (*cpu_init)(struct device_node *, unsigned int);

  30:         int             (*cpu_init_idle)(struct device_node *, unsigned int);

  31:         int             (*cpu_prepare)(unsigned int);

  32:         int             (*cpu_boot)(unsigned int);

  33:         void            (*cpu_postboot)(void);

  34: #ifdef CONFIG_HOTPLUG_CPU

  35:         int             (*cpu_disable)(unsigned int cpu);

  36:         void            (*cpu_die)(unsigned int cpu);

  37:         int             (*cpu_kill)(unsigned int cpu);

  38: #endif

  39: #ifdef CONFIG_ARM64_CPU_SUSPEND

  40:         int             (*cpu_suspend)(unsigned long);

  41: #endif

  42: };

   1: /* arch/arm64/kernel/cpu_ops.c */

   2:  

   3: static const struct cpu_operations *supported_cpu_ops[] __initconst = {

   4: #ifdef CONFIG_SMP

   5:         &smp_spin_table_ops,

   6: #endif

   7:         &cpu_psci_ops,

   8:         NULL,

   9: };

   1: /* spin-table: arch/arm64/boot/dts/apm-storm.dtsi */

   2: cpus {

   3:         ...

   4:         cpu@000 {

   5:                 ...

   6:                 enable-method = "spin-table";

   7:                 cpu-release-addr = <0x1 0x0000fff8>;

   8:         };

   9:         ...

  10: };

  11:  

  12: /* or psci: arch/arm64/boot/dts/thunder-88xx.dtsi */

  13: cpus {

  14:         ...

  15:         cpu@000 {

  16:                 ...

  17:                 enable-method = "psci";

  18:         };

  19:         ...

  20: };

   1: /* arch/arm64/kernel/cpu_ops.c */

   2: const struct cpu_operations *cpu_ops[NR_CPUS];

   1: const struct cpu_operations smp_spin_table_ops = {

   2:         .name           = "spin-table",

   3:         .cpu_init       = smp_spin_table_cpu_init,

   4:         .cpu_prepare    = smp_spin_table_cpu_prepare,

   5:         .cpu_boot       = smp_spin_table_cpu_boot,

   6: };

   1: static int smp_spin_table_cpu_init(struct device_node *dn, unsigned int cpu)

   2: {

   3:         /*

   4:          * Determine the address from which the CPU is polling.

   5:          */

   6:         if (of_property_read_u64(dn, "cpu-release-addr",

   7:                                  &cpu_release_addr[cpu])) {

   8:                 pr_err("CPU %d: missing or invalid cpu-release-addr property\n",

   9:                        cpu);

  10:  

  11:                 return -1;

  12:         }

  13:  

  14:         return 0;

  15: }

   1: static int smp_spin_table_cpu_prepare(unsigned int cpu)

   2: {

   3:         __le64 __iomem *release_addr;

   4:  

   5:         if (!cpu_release_addr[cpu])

   6:                 return -ENODEV;

   7:  

   8:         /*

   9:          * The cpu-release-addr may or may not be inside the linear mapping.

  10:          * As ioremap_cache will either give us a new mapping or reuse the

  11:          * existing linear mapping, we can use it to cover both cases. In

  12:          * either case the memory will be MT_NORMAL.

  13:          */

  14:         release_addr = ioremap_cache(cpu_release_addr[cpu],

  15:                                      sizeof(*release_addr));

  16:         if (!release_addr)

  17:                 return -ENOMEM;

  18:  

  19:         /*

  20:          * We write the release address as LE regardless of the native

  21:          * endianess of the kernel. Therefore, any boot-loaders that

  22:          * read this address need to convert this address to the

  23:          * boot-loader's endianess before jumping. This is mandated by

  24:          * the boot protocol.

  25:          */

  26:         writeq_relaxed(__pa(secondary_holding_pen), release_addr);

  27:         __flush_dcache_area((__force void *)release_addr,

  28:                             sizeof(*release_addr));

  29:  

  30:         /*

  31:          * Send an event to wake up the secondary CPU.

  32:          */

  33:         sev();

  34:  

  35:         iounmap(release_addr);

  36:  

  37:         return 0;

  38: }

   1: /* arch/arm64/kernel/head.S */

   2:  

   3:         .align  3

   4: 1:      .quad   .

   5:         .quad   secondary_holding_pen_release

   6:  

   7:         /*

   8:          * This provides a "holding pen" for platforms to hold all secondary

   9:          * cores are held until we're ready for them to initialise.

  10:          */

  11: ENTRY(secondary_holding_pen)

  12:         bl      el2_setup                       // Drop to EL1, w20=cpu_boot_mode

  13:         bl      __calc_phys_offset              // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET

  14:         bl      set_cpu_boot_mode_flag

  15:         mrs     x0, mpidr_el1

  16:         ldr     x1, =MPIDR_HWID_BITMASK

  17:         and     x0, x0, x1

  18:         adr     x1, 1b

  19:         ldp     x2, x3, [x1]

  20:         sub     x1, x1, x2

  21:         add     x3, x3, x1

  22:         ldr     x4, [x3]

  23: pen:    cmp     x4, x0

  24:         b.eq    secondary_startup

  25:         wfe

  26:         b       pen

  27: ENDPROC(secondary_holding_pen)

   1: /*

   2:  * Write secondary_holding_pen_release in a way that is guaranteed to be

   3:  * visible to all observers, irrespective of whether they're taking part

   4:  * in coherency or not.  This is necessary for the hotplug code to work

   5:  * reliably.

   6:  */

   7: static void write_pen_release(u64 val)

   8: {

   9:         void *start = (void *)&secondary_holding_pen_release;

  10:         unsigned long size = sizeof(secondary_holding_pen_release);

  11:  

  12:         secondary_holding_pen_release = val;

  13:         __flush_dcache_area(start, size);

  14: }

  15:  

  16: static int smp_spin_table_cpu_boot(unsigned int cpu)

  17: {

  18:         /*

  19:          * Update the pen release flag.

  20:          */

  21:         write_pen_release(cpu_logical_map(cpu));

  22:  

  23:         /*

  24:          * Send an event, causing the secondaries to read pen_release.

  25:          */

  26:         sev();

  27:  

  28:         return 0;

  29: }